1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor integrated circuits. More particularly, the present invention relates to a method of manufacturing a damascene MOSFET (metal oxide semiconductor field effect transistor) gate structure.
2. Description of the Related Arts
Recently, as the manufacturing techniques of semiconductor integrated circuits develop, the number of elements in a chip has increased. The gate length of the transistor has scaled down to less than 100 nm, with the gate oxide thickness usually less than 3 nm. The conventional manufacturing method for a MOSFET gate structure comprises forming a shallow trench isolation (STI) composed of silicon dioxide on a silicon substrate to define an active area, forming a gate oxide layer and a polysilicon layer sequentially, covering the polysilicon layer with a hard mask, defining a polysilicon gate by photolithography and etching, performing implantation of the lightly doped drain, and forming sidewall spacers.
The conventional manufacturing method usually utilizes repeated processes of deposition, photolithography and etching; however, the production of hard masks is costly. With the need for more precise element, the gate manufacturing method becomes more difficult. In addition, over-etching of the oxide layer may result in damage to the underlying silicon substrate when the polysilicon layer and oxide layer are removed from the non-gate area. Accordingly, the uneven surface of the substrate may cause poor contact in subsequent process. If the etching step is not completed, a gate to gate or gate to bitline stringer may appear, and short circuit may occur. There is still a need to solve the aforementioned drawbacks of the conventional manufacturing method.